Physical Design Engineer Broadcom
Overview
Lead physical layout engineering for next generation ASIC products focusing on parallel interfaces. Develop advanced 2.5D and 3D interconnects while collaborating with R&D and manufacturing partners. Drive innovation in high-speed signal interconnects and new technology pathsfinding.
What You'll Do11
- 1Design implement power grids 2.5D and 3D die-die interconnects
- 2Perform DRC LVS and electrical checking
- 3Automate common layout processes and design steps
- 4Develop high-speed signal interconnects with SI and PI engineers
- 5Conduct electrical analysis and optimize ubump and RDL patterns
- 6Evaluate and develop new 2.5D and 3D interconnect technologies
- 7Create technology and testchip roadmaps emphasizing advanced packaging
- 8Manage multiple concurrent customers under tight deadlines
- 9Provide technical guidance for projects with limited information
- 10Utilize TCL and Python scripting to automate routine tasks
- 11Collaborate with global organization and customer base
Requirements8
- 1Independent self-starter comfortable managing diverse customer workloads
- 2Proven ability to guide teams through ambiguous situations
- 3Expertise with IC Package and PCB layout databases and tools
- 4Strong bachelor's degree in Electrical Engineering or Computer Science with 12+ years experience
- 5Master's degree in Electrical Engineering or Computer Science with 10+ years experience
- 612+ years related work experience or 10+ years with master's
- 712+ years related work experience for bachelor's holders
- 812+ years related work experience for master's holders
Salary Insight
$144 - $230k per year
Location
Required Skills
Similar open positions
Explore active roles that match your skills and interests.
Qualcomm
VerifiedPhysical Design Engineer Qualcomm
Qualcomm seeks senior Physical Design Engineers to lead SoC and ASIC design initiatives. Candidates will own complex digital design flows delivering high-performance power-efficient products across GPU camera multimedia DDR modem audio and other cutting‑edge semiconductor solutions. This role offers collaboration with world‑class verification integration and physical design teams to push technology boundaries.
100 Intel Corporation
VerifiedAnalog Layout Design Engineer
You will own the full lifecycle of analog layout design for Intel's cutting-edge chips, delivering complex layouts that meet demanding performance, area, and reliability targets. You will work with Cadence Virtuoso and Calibre/ICV to verify designs at scale, collaborating with circuit design, process technology, and package teams. Your work directly shapes Intel's next-generation products, and you will drive innovative layout methodologies that improve productivity. This role offers deep exposure to advanced CMOS technologies and high-voltage rules, with a clear path for technical growth.
Efficient Computer
VerifiedLead Physical Design Engineer SOC Top Lead
Efficient develops energy efficient general purpose computer processor. Lead engineer drives SOC top for next generation SoCs. Own full chip from block integration to tapeout ready GDS. Influence product evolution from development to market release. Shape future of computing at the edge.
The University of Texas at Austin
VerifiedPrincipal Mixed Signal Engineer Texas Institute for Electronics
Lead development of next generation digital subsystems and compute fabrics for 2.5D/3D microsystems enabling scalable high bandwidth integration across AI HPC and wireless acceleration platforms. Define architecture specifications collaborate with teams optimize performance and engage semiconductor partners to shape ecosystem directions.

Braintree Technology Solutions
VerifiedPCB Layout Engineer, High-Speed Digital & Allegro
Own end-to-end PCB layout for complex, high-density designs powering data center server boards. Partner with hardware engineers to deliver high-speed digital layouts for interfaces like HBM, DDR4/5, PCIe Gen 5/6, and USB 3.2+. Define design rules that balance signal integrity, manufacturability, and thermal performance. This contract role in Menlo Park puts you at the core of next-gen server technology.
1000 Micron Technology, Inc.
VerifiedSoC Physical Design Engineer
Senior Member of Technical Staff leads physical design of SoC logic/base die from netlist to GDSII within Heterogeneous Integration Group. Owns implementation across multiple product generations and drives performance power area targets.