Analog Layout Design Engineer
Overview
You will own the full lifecycle of analog layout design for Intel's cutting-edge chips, delivering complex layouts that meet demanding performance, area, and reliability targets. You will work with Cadence Virtuoso and Calibre/ICV to verify designs at scale, collaborating with circuit design, process technology, and package teams. Your work directly shapes Intel's next-generation products, and you will drive innovative layout methodologies that improve productivity. This role offers deep exposure to advanced CMOS technologies and high-voltage rules, with a clear path for technical growth.
What You'll Do8
- 1Design complex layouts of analog signal circuits based on detailed design specs, using Cadence Virtuoso.
- 2Run design verification checks including process design rules, electron migration, IR drop, ESD, and reliability assessments.
- 3Develop floorplans, power grids, ESD structures, and bump layouts to meet performance and electrical specs.
- 4Perform floor planning and signal planning for complex analog circuits, optimizing for area, power, reliability, and performance.
- 5Drive implementation of innovative analog layout methodologies to boost productivity and layout quality.
- 6Troubleshoot layout design, tool, flow, and methodology issues across the design lifecycle.
- 7Collaborate with cross-disciplinary teams to align on design requirements and negotiate tradeoffs.
- 8Apply best practices for common-centroid, interdigitation, and symmetry-based layouts to minimize mismatch and variation.
Requirements8
- 1Bachelor's degree or equivalent in Electrical Engineering, Computer Engineering, or related field with 3+ years of experience, or Master's degree with 2+ years.
- 2Analog device and metal layout fundamentals, including analog/mixed-signal design basics.
- 3Experience with Cadence Virtuoso layout suite and Calibre/ICV DRC for design verification.
- 4Knowledge of CMOS technologies and high-voltage design rules.
- 5Floor planning and hierarchical layout planning for analog and mixed-signal blocks.
- 6Conducting performance verification and debugging layout-related issues.
- 7Understanding of analog layout effects: mismatch, parasitics, IR drop, electromigration (EM), and coupling.
- 8Experience with parasitic-aware design, using extraction tools like extract/SPEF and simulation teams.
Salary Insight
$122 - $173k per year
Location
Required Skills
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