Lead Physical Design Engineer SOC Top Lead
Overview
Efficient develops energy efficient general purpose computer processor. Lead engineer drives SOC top for next generation SoCs. Own full chip from block integration to tapeout ready GDS. Influence product evolution from development to market release. Shape future of computing at the edge.
What You'll Do11
- 1Full-chip integration: floorplanning power planning macro/hard IP placement and block partitioning at top level ensuring convergence across hierarchical blocks
- 2Timing closure: full-chip STA across all corners/modes including cross-boundary timing and chip-level constraint SDC ownership
- 3Power: full-chip power planning PDN design analysis IR drop EM rail architecture and power-gating strategy coordination
- 4Physical verification: DRC LVS antenna closure seal ring integration and ECO cycle coordination
- 5Signal integrity & noise: crosstalk di/t and chip-level noise closure around high speed IO and PLL analog boundaries
- 6Clock & reset architecture: top-level clock tree strategy across domains including CTS coordination with block owners
- 7DFT integration: chip-level scan stitching MBIST JTAG integration and ATPG test coverage closure
- 8Package/IO co-design: bump/ball map coordination IO ring planning and package aware floorplanning
- 9Tapeout readiness: sign-off checklist ownership timing power physical reliability and final GDS handoff
- 10Cross-team coordination: single point of contact between block-level PD owners DV DFT package engineering and architecture on convergence tradeoffs and schedule risk
- 11Technical leadership: mentor block-level PD engineers on convergence best practices set methodology for chip-top closure
Requirements12
- 1Master's degree in Electrical Engineering with 5+ years industry experience or PhD with 3+ years industry experience
- 28-12+ years physical design experience with at least 2-3 full tapeouts at chip-top/SoC integration level
- 3Deep hands-on experience with advanced nodes
- 4Strong PDN/IR-drop/EM analysis proficiency Voltus or equivalent
- 5Experience with chip-level DFT integration scan stitching MBIST JTAG
- 6Familiarity with package co-design flip-chip/BGA C4 bumps ball map
- 7Tool fluency Innovus ICC2 Tempus PrimeTime RedHawk Calibre
- 8Demonstrated ability to lead technically without direct reports driving alignment across engineers and teams
- 9Experience with non-standard novel architectures dataflow tiled NoC-based systems
- 10Excellent scripting skills in TCL shell and Python
- 11Knowledge of computer architecture physical design ASIC implementation full chip sign off convergence circuit design device physics deep sub-micron technology knowledge
- 12Proficiency integrating analog or mixed-signal macros on top-level designs
Salary Insight
$200 - $250k per year
Location
Required Skills
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