CPU Physical Design Engineer Intel
Overview
Design and lead physical implementation of custom CPU cores from RTL to GDS. Own end‑to‑end design flow including synthesis, placement, routing, and verification. Collaborate with cross‑functional teams to deliver high‑performance, power‑efficient processors for client server and AI workloads. Differentiate yourself by driving innovation in microprocessor architecture and design automation.
What You'll Do8
- 1Perform physical design implementation of custom CPU designs from RTL to GDS to create a production‑ready database
- 2Conduct synthesis place and route clock tree synthesis floor planning static timing analysis power and noise analysis
- 3Lead verification and signoff activities such as formal equivalence verification static timing analysis reliability verification layout verification electrical rule checking and structural design checking
- 4Analyze results and recommend improvements to enhance CPU microarchitectures in partnership with logic circuit architecture and design automation groups
- 5Apply CPU specific expertise in clock design timing closure coverage analysis multi‑power domain analysis structured placement routing synthesis and DFT
- 6Work with EDA vendors to develop and enhance tools for high‑speed low‑power synthesizable CPU design
- 7Optimize CPU designs to improve power frequency and area metrics
- 8Contribute to evolving physical design methodologies and flow automation processes
Requirements11
- 1Bachelor of Science in Computer Engineering Electrical Engineering or related field with 3+ years of relevant experience or M.S. with 2+ years of experience
- 22+ years experience in synthesis of a digital logic block or partition
- 32+ years experience with integrated circuit design tools including logic synthesis place and route static timing analysis and design closure
- 4Proficiency in PV convergence static timing and power analysis
- 5Expertise in chip physical design verification covering formal equivalence electrical rules DRC LVS and noise flow
- 6Strong TCL scripting ability
- 7Prior solo ownership of a CPU block synthesis and PNR effort
- 8Knowledge of floor‑planning routing techniques clock distribution and tape‑out experience on advanced nodes
- 9Familiarity with static timing analysis noise analysis and reliability verification techniques
- 10Experience generating and resolving timing constraints at chip or block level for CPU cores
- 11Collaboration with clocking and full‑chip design teams to balance timing power and partitioning
Salary Insight
$106 - $200k per year
Location
Required Skills
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