Intel
IntelVerified Source

CPU Physical Design Engineer Intel

106K–200K
Onsite · Austin, Texas
Posted August 12, 2026
payroll

Overview

Design and lead physical implementation of custom CPU cores from RTL to GDS. Own end‑to‑end design flow including synthesis, placement, routing, and verification. Collaborate with cross‑functional teams to deliver high‑performance, power‑efficient processors for client server and AI workloads. Differentiate yourself by driving innovation in microprocessor architecture and design automation.

What You'll Do8

  • 1Perform physical design implementation of custom CPU designs from RTL to GDS to create a production‑ready database
  • 2Conduct synthesis place and route clock tree synthesis floor planning static timing analysis power and noise analysis
  • 3Lead verification and signoff activities such as formal equivalence verification static timing analysis reliability verification layout verification electrical rule checking and structural design checking
  • 4Analyze results and recommend improvements to enhance CPU microarchitectures in partnership with logic circuit architecture and design automation groups
  • 5Apply CPU specific expertise in clock design timing closure coverage analysis multi‑power domain analysis structured placement routing synthesis and DFT
  • 6Work with EDA vendors to develop and enhance tools for high‑speed low‑power synthesizable CPU design
  • 7Optimize CPU designs to improve power frequency and area metrics
  • 8Contribute to evolving physical design methodologies and flow automation processes

Requirements11

  • 1Bachelor of Science in Computer Engineering Electrical Engineering or related field with 3+ years of relevant experience or M.S. with 2+ years of experience
  • 22+ years experience in synthesis of a digital logic block or partition
  • 32+ years experience with integrated circuit design tools including logic synthesis place and route static timing analysis and design closure
  • 4Proficiency in PV convergence static timing and power analysis
  • 5Expertise in chip physical design verification covering formal equivalence electrical rules DRC LVS and noise flow
  • 6Strong TCL scripting ability
  • 7Prior solo ownership of a CPU block synthesis and PNR effort
  • 8Knowledge of floor‑planning routing techniques clock distribution and tape‑out experience on advanced nodes
  • 9Familiarity with static timing analysis noise analysis and reliability verification techniques
  • 10Experience generating and resolving timing constraints at chip or block level for CPU cores
  • 11Collaboration with clocking and full‑chip design teams to balance timing power and partitioning

Salary Insight

$106 - $200k per year

Location

Typeonsite
LocationAustin, Texas

Required Skills

CPU Physical DesignRTL to GDSLogic SynthesisPlace and RouteClock Tree SynthesisFloor PlanningStatic Timing AnalysisPower DistributionReliability VerificationNoise AnalysisFormal Equivalence VerificationDRCLVSTCL Scripting
Share:

Similar open positions

Explore active roles that match your skills and interests.

100 Intel Corporation

100 Intel Corporation

16d agoPortland, Oregonpayroll

Mid-Level Physical Design Engineer CPU - Intel

Design and deliver high-performance CPU cores for client server IoT and AI platforms. Lead RTL-to-GDS flow ownership while collaborating with cross-functional teams. Build depth in physical design and SoC development. Strong growth opportunities available.

122K–232K
SynopsysCadenceLogic synthesis+6 more

Google

17h agoAustin, Texaspayroll

CPU Physical Design Engineer - Google Silicon

Own block-level physical design for Google's custom silicon, from synthesis through signoff, targeting high-performance, low-power CPUs at 5nm and below. Collaborate with RTL, Architecture, and DFT teams to align constraints and resolve timing, congestion, and power issues. Drive design convergence with industry-standard tools like Synopsys and Cadence. This role requires deep expertise in Place & Route and STA to deliver silicon that powers Google's direct-to-consumer products.

138K–197K
Digital Physical Design ImplementationSynthesisPlace and Route+5 more
100 Intel Corporation

100 Intel Corporation

2d agoAustin, Texaspayroll

Senior CPU Pre-Silicon Verification Engineer at Intel

Lead functional verification of CPU logic to ensure design meets specifications. Drive verification environment and collaborate with CPU architects to improve microarchitectural verification. Aim to ship world-changing processor technology. Join Intel's elite engineering organization shaping the future of computing.

164K–312K
UVMSystem VerilogEDA tools+8 more

Qualcomm

20h agoSan Diego, Californiapayroll

Physical Design Engineer Qualcomm

Qualcomm seeks senior Physical Design Engineers to lead SoC and ASIC design initiatives. Candidates will own complex digital design flows delivering high-performance power-efficient products across GPU camera multimedia DDR modem audio and other cutting‑edge semiconductor solutions. This role offers collaboration with world‑class verification integration and physical design teams to push technology boundaries.

116K–173K
Physical design flowFloorplanningClock Tree Synthesis+3 more
1000 Micron Technology, Inc.

1000 Micron Technology, Inc.

20h agoDallas, Texaspayroll

SoC Physical Design Engineer

Senior Member of Technical Staff leads physical design of SoC logic/base die from netlist to GDSII within Heterogeneous Integration Group. Owns implementation across multiple product generations and drives performance power area targets.

177K–334K
Cadence InnovusSynopsys ICC2PrimeTime+9 more
100 Intel Corporation

100 Intel Corporation

7d agoPortland, Oregonpayroll

Server CPU SoC Architect - Intel | CPU Architecture Jobs

Define and drive CPU architecture for Intel's server and edge products, balancing performance, power, frequency, and area. You will model SoC designs, explore novel approaches, and collaborate across teams to shape future CPU implementations. Your work directly impacts Intel's leadership in AI and cloud-to-edge technology. This role offers a hybrid work model and a chance to influence cross-functional roadmaps.

142K–269K
CPU architectureSoC architecturePerformance modeling+7 more