Principal Mixed Signal Engineer Texas Institute for Electronics
Overview
Lead development of next generation digital subsystems and compute fabrics for 2.5D/3D microsystems enabling scalable high bandwidth integration across AI HPC and wireless acceleration platforms. Define architecture specifications collaborate with teams optimize performance and engage semiconductor partners to shape ecosystem directions.
What You'll Do5
- 1Design and develop high speed mixed signal I/O circuits for UCIe 2.5D and 3.0D die to die interfaces enabling robust low latency chiplet interconnect across AI HPC and defense platforms
- 2Architect and optimize SerDes clock data recovery equalization and transceiver circuits for high speed die to die and chip to chip links including UCIe PCIe physical layers
- 3Collaborate with packaging EDA and system modeling teams to co optimize mixed signal I/O performance accounting for signal integrity power delivery crosstalk and thermal effects unique to 3DHI
- 4Lead silicon bring up bench characterization and production testing of high speed I/O and mixed signal circuits developing test methodologies ATE programs and yield improvement strategies from prototype through volume production
- 5Engage with industry partners and standards bodies such as UCIe Consortium to influence specification development and ensure physical layer implementations remain standards aligned
Requirements5
- 1M.S. in Electrical Engineering with emphasis on analog mixed signal or high speed circuit design or equivalent practical experience
- 212+ years of experience in mixed signal or high speed I/O circuit design for SoC ASIC with direct involvement in SerDes UCIe or comparable die to die chip to chip interface IP
- 3Deep expertise in high speed transceiver design including TX RX front ends CDR equalization PLLs DLLs and signal integrity analysis for multi gbps links
- 4Hands on experience with silicon bring up lab characterization using high speed oscilloscopes BER testers network analyzers and production test development on ATE platforms
- 5Proficiency with analog/mixed signal EDA tools Cadence Virtuoso Spectre Synopsys HSPICE Ansys HFSS SIwave and parasitic aware simulation methodologies
Salary Insight
Salary not disclosed in listing
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