MetaVerified Source

Compiler Architect - MTIA Software Technical Leadership

219K–301K
Onsite · San Francisco, California
Posted August 7, 2026
payroll

Overview

Principal-level Compiler Architect leads technical strategy for MTIA compiler infrastructure enabling efficient code generation on custom AI accelerators. Defines architecture for graph compilers and optimization spanning ML workload analysis to hardware-software co-design. Drives performance improvements and collaborates with hardware teams to influence accelerator decisions. Produces clear design documents and mentors engineers across the organization.

What You'll Do11

  • 1Define and own compiler architecture and technical roadmap for MTIA including graph compilers and optimization strategies
  • 2Solve complex compiler optimization challenges spanning operator fusion and memory planning
  • 3Design extensible compiler frameworks and intermediate representations for rapid iteration
  • 4Drive performance improvements by eliminating bottlenecks across compiler stack
  • 5Partner with MTIA hardware teams on co-design influencing accelerator architecture decisions
  • 6Establish compiler correctness and reliability practices for production-quality code generation
  • 7Collaborate with ML framework teams to integrate MTIA compiler infrastructure with PyTorch
  • 8Evaluate and adopt state-of-the-art compiler technologies such as MLIR
  • 9Mentor engineers conducting architecture reviews and fostering technical excellence
  • 10Communicate complex architecture concepts to technical and non-technical audiences
  • 11Lead cross-functional initiatives defining metrics and managing dependencies across teams

Requirements15

  • 1Bachelor's degree in Computer Science or equivalent practical experience
  • 212+ years of experience in compiler development for accelerators or custom silicon
  • 3Architected production compiler infrastructure for ML accelerators GPUs or custom silicon
  • 4Experience with compiler IRs optimization passes and code generation techniques
  • 5Led multi-year initiatives defining metrics and executing across organizational boundaries
  • 6Developed high-performance systems software in C++ with low-level optimization knowledge
  • 7Influenced technical direction through written proposals design reviews and stakeholder alignment
  • 8Master's or PhD degree in Computer Science or related field
  • 9Track record applying AI tools to redesign engineering workflows improving efficiency
  • 10Experience with graph-level optimizations operator fusion memory planning scheduling for ML workloads
  • 11Contributed to compiler or ML systems via publications open-source projects or standards bodies
  • 12Defined performance benchmarks and correctness validation for compiler infrastructure
  • 13Deep understanding of transformer CNN architectures and computational patterns
  • 14Adhered to ethical AI practices including bias mitigation and quality reviews
  • 15Experience with ML compiler stacks such as MLIR XLA TVM Glow or similar frameworks

Salary Insight

$219 - $301k per year

Location

Typeonsite
LocationSan Francisco, California

Required Skills

C++Compiler DevelopmentMLIRXLATVMGlowHardware-Software Co-DesignGraph-Level OptimizationsOperator FusionMemory PlanningSchedulingPerformance OptimizationPyTorch Integration
Share:

Similar open positions

Explore active roles that match your skills and interests.

DensityAI

1d agoSan Jose, Californiapayroll

MLIR Compiler Engineer - DensityAI

Lead ownership of MLIR dialect design and lowering passes for AI accelerator. Define high-level tensor IR async streaming semantics and sharded-tensor types bridging ML frameworks to silicon. Drive DensityAI AI accelerator program from silicon to scale-out. Build AI-assisted tool flows to accelerate compiler development.

200K–360K
mlirpythonaws+2 more
NVIDIA

NVIDIA

1d agoAustin, Texaspayroll

Senior Compiler Engineer Infrastructure at NVIDIA

You will align NVIDIA's compiler codebases with open-source ecosystems, focusing on LLVM, Clang, and MLIR. Own the reconciliation of downstream repositories with upstream projects, building tooling that scales across thousands of engineers. You will join the Compute Compiler Team, reporting to the director of compiler infrastructure, and collaborate with compiler developers and CI teams. This role stands out for its dual focus on open-source stewardship and developer productivity, with access to NVIDIA's GPU stack.

152K–242K
C++Open-source compiler frameworksLLVM+9 more

DensityAI

1d agoSan Jose, Californiapayroll

LLVM Backend Compiler Engineer - DensityAI

Lead ownership of LLVM backend development for custom accelerator ISA focusing on instruction selection register allocation scheduling and linker support across scalar vector and floating point pipelines. Drive AI-assisted tool flows to accelerate compiler development and performance tuning while collaborating with chip-design and software teams to deliver DensityAI's AI accelerator program from silicon to scale-out.

200K–360K
LLVM backend developmentTableGenInstruction selection+6 more

Meta

10d agoSan Jose, Californiapayroll

Machine Learning SoC Architect at Meta

Meta seeks a Machine Learning SoC Architect to lead ASIC design for silicon underpinning AI and data center workloads at scale. You will define architecture performance modeling and roadmap while partnering with silicon and software teams. This role drives innovation in custom silicon solutions shaping the future of social technology.

212K–294K
C++PythonASIC performance modeling+4 more

Meta

15d agoSan Francisco, Californiapayroll

Machine Learning SoC Architect at Meta

Meta seeks a Machine Learning SoC Architect to lead custom silicon design for data centers. You will define architecture performance modeling and roadmap while partnering with cross functional teams. This role drives innovation in ASICs for AI and data center workloads.

212K–294K
Computer ArchitectureASIC Performance ModelingC+++4 more
Intel

Intel

1d agoSan Jose, Californiapayroll

AI Infrastructure Engineer Intel

Performance‑obsessed AI Infrastructure Engineer at Intel in San Jose, California. You will drive inference performance and redefine peak performance on Intel’s next‑generation GPU architectures.

170K–315K
C++PythonGPU Computing+8 more