Staff Design Verification Engineer, CPU Core
Overview
You will own verification for high-performance out-of-order CPU core areas, including Frontend, Midcore, Load-Store Unit, and Hardware Prefetch. Working with SystemVerilog and UVM, you will drive strategy, debug, and coverage closure for complex microarchitectural features. You will partner with architecture and RTL teams to catch risks early and raise quality across the core. This role offers the chance to influence methodology for next-generation RISC-V processors at SiFive.
What You'll Do7
- 1Own verification planning and execution for high-performance CPU core areas, including Frontend, Midcore, Load-Store Unit, and Hardware Prefetch.
- 2Drive block-level and core-level verification planning, debug, coverage analysis, and closure for features like instruction fetch, branch prediction, and pipeline interactions.
- 3Define verification strategies for load/store ordering, hazard handling, memory consistency, and hardware prefetch correctness using UVM and SystemVerilog.
- 4Develop robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models to expose corner cases.
- 5Partner with architecture and design teams to review specifications, identify ambiguity, and improve debugability early.
- 6Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
- 7Contribute reusable methodology, infrastructure, and technical guidance to improve productivity across future core generations.
Requirements10
- 17+ years in ASIC, CPU/core, or SoC design verification.
- 27+ years of hands-on experience with SystemVerilog and UVM-based verification.
- 3Direct experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture.
- 4Experience with high-performance CPU areas: Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
- 5Strong knowledge of verification flow methodology, including test planning, constrained-random generation, failure analysis, and coverage closure.
- 6Strong debug skills and ability to translate architectural intent into effective verification strategy.
- 7BS/MS in EE, CE, or CS.
- 8Experience with out-of-order core verification (preferred).
- 9Experience with formal verification or emulation for high-risk verification problems (preferred).
- 10Familiarity with Python, C/C++, or other scripting languages for DV infrastructure (preferred).
Salary Insight
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