Principal Design Verification Engineer – CPU Subsystem Power Management
Overview
SiFive seeks a Principal Design Verification Engineer to lead verification of CPU-subsystem power-management functionality across complex SoC and subsystem environments. The role focuses on delivering data-center-grade quality resiliency and signoff readiness while defining architecture-aware verification strategies early and identifying integration risks. This principal tech-lead will drive verification across core cluster LLC and uncore power-management behavior including DVFS live retention clock gating warm reset power gating and subsystem interactions. Collaboration with architecture RTL formal and performance teams ensures design intent is captured and debugability is prioritized. Success is measured by early detection of critical bugs in power-state transitions reset sequencing retention and clocking behavior and fostering reusable methodologies that elevate verification quality across the power-management DV organization.
What You'll Do10
- 1Lead verification planning and execution for CPU-subsystem power-management features from unit and block level through subsystem integration and signoff
- 2Define verification strategies test plans assertions checkers coverage models and closure criteria for complex power-state transitions clock/reset sequencing retention behavior DVFS scenarios warm-reset flows and multi-domain interactions
- 3Drive verification across multiple bench contexts including CoreIP PMC unit-level and broader PM unit and uncore environments
- 4Own high-value stress corner-case and long-run scenarios exposing failures in power-state sequencing asynchronous clock relationships retention recovery reset interactions wakeup behavior and activity-monitor correctness
- 5Partner with architecture RTL DV and infrastructure teams to review specifications reduce ambiguity early and improve debugability and verification completeness
- 6Drive efficient failure analysis and root-cause debug across specification RTL verification infrastructure assertions and stimulus
- 7Apply appropriate verification methods simulation formal techniques power-aware verification and emulation for subsystem-level signoff
- 8Contribute reusable methodology automation and verification infrastructure that improve quality and productivity across the power-management DV organization
- 9Mentor engineers and provide technical leadership for difficult subsystem-level debug and closure challenges
- 10Help define signoff expectations suitable for data-center-grade CPU subsystems focusing on correctness across power states reset behaviors retention flows and integration boundaries
Requirements12
- 15+ years building ETL pipelines with Spark and Airflow
- 212+ years relevant experience in CPU subsystem or SoC functional verification
- 3Strong experience in CPU-subsystem or SoC power-management verification including clock/reset behavior power-state transitions retention gating and multi-domain interactions
- 4Solid software scripting and automation skills in Python or similar languages for DV infrastructure and workflow scalability
- 5Direct experience verifying CPU-subsystem power-management features such as DVFS power gating retention warm reset and clock-gating behavior across core cluster LLC and uncore domains
- 6Experience with PMC- or power-controller-centric verification including unit-level benches and standalone verification flows
- 7Developing or reviewing checkers for live retention CCidle tile or cluster live retention and related PM correctness checks
- 8Formal verification power-aware simulation emulation or related advanced verification techniques for subsystem-level signoff
- 9Experience with subsystem integration issues involving resets clock-domain interactions coherency-sensitive traffic and performance-sensitive power-state transitions in high-performance CPU environments
- 10Demonstrated ability to influence verification methodology and technical direction beyond immediate ownership
- 11Minimum Qualifications BS MS or PhD in Electrical Engineering Computer Engineering Computer Science or related field
- 12Strong hands-on experience with SystemVerilog-based verification scalable verification planning assertions checkers coverage strategy and debug workflows for complex hardware subsystems
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