Principal Design Verification Engineer, CPU Core LSU
Overview
You will lead verification strategy and execution for the CPU Core Load-Store Unit (LSU) in a high-performance out-of-order core, defining architecture-aware plans that catch the highest-risk microarchitectural issues early. You will own block-level and core-level verification, covering load/store ordering, cache coherency, and memory consistency. You will partner with architecture, RTL, formal, and performance teams to ensure design intent is captured and signoff quality is achieved with scalable methodology. This role distinguishes itself by focusing on the most complex LSU and memory-subsystem verification challenges, with direct impact on future generations of SiFive cores.
What You'll Do9
- 1Lead verification strategy for the LSU, including block-level and core-level planning, execution, debug, coverage analysis, and closure.
- 2Define verification strategies for complex LSU behaviors: load/store ordering, hazard handling, barrier and fence behavior, memory consistency, and weak memory ordering.
- 3Drive verification of cache-facing LSU behavior including cache hit/miss, snoops, evictions, and coherency state interactions across L1 and downstream memory hierarchy.
- 4Own corner cases involving overlapping accesses, false sharing, outstanding loads/stores to the same cache line, data forwarding, and speculative execution repair.
- 5Develop high-value checkers, scoreboards, assertions, and coverage models that expose coherency and consistency corner cases.
- 6Apply simulation, formal techniques, and emulation to improve quality and debug efficiency on large CPU verification workloads.
- 7Partner with architects and designers from feature definition to review specs and improve debugability before implementation hardens.
- 8Drive root-cause analysis across specification, RTL, test content, assertions, and verification infrastructure.
- 9Mentor engineers and shape reusable verification approaches for future CPU cores and memory subsystems.
Requirements10
- 1BS, MS, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- 212+ years in CPU/core or SoC functional verification, with depth for a Principal / T6 role.
- 38+ years direct experience on memory management verification, including hypervisor and virtualization.
- 4Direct experience with out-of-order core verification and strong understanding of CPU microarchitecture.
- 5Deep expertise in Load-Store Unit verification, memory ordering, and consistency.
- 6Strong understanding of cache-coherent systems and memory hierarchy behavior.
- 7Strong knowledge of verification methodology: test planning, stimulus, coverage analysis, and closure.
- 8Strong debug skills and ability to translate architectural intent into verification strategy.
- 9Seasoned developer using object-oriented programming principles.
- 105+ years experience with formal verification of LSU or memory-subsystem properties.
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