Senior RTL Design Engineer CPU Frontend
Overview
SiFive seeks a Senior RTL Design Engineer to lead CPU frontend design at scale. You will own the creation of new features and performance improvements within RISC-V CPU core generators using Chisel. This role drives architectural decisions and collaborates across teams to deliver high-performance processors. The position offers a unique chance to shape cutting‑edge silicon while contributing to a mission focused on advancing RISC‑V adoption.
What You'll Do9
- 1Architect and design new features and performance enhancements in RISC‑V CPU cores using Chisel
- 2Integrate design content into SiFive’s Chisel/FIRRTL framework and improve automation for documentation and testing
- 3Conduct sandbox verification and develop verification test plans with the verification team
- 4Partner with physical implementation engineers to optimize layout for frequency area and power targets
- 5Collaborate with performance modeling specialists to explore and refine microarchitectural designs
- 6Lead microarchitecture specification and ensure knowledge sharing through comprehensive documentation
- 7Mentor junior engineers and champion collaborative design practices
- 8Drive continuous improvement of hardware verification methodologies and test infrastructure
- 9Contribute to open‑source hardware projects and community standards
Requirements12
- 1BS/MS degree in computer science or related field or equivalent experience
- 23+ years of design experience focusing on CPU RTL
- 3Proven expertise with instruction fetch decode branch prediction coherent caches cache prefetching TLBs
- 4Strong proficiency in Verilog System Verilog or VHDL for RTL development
- 5Experience with functional programming concepts templated metaprogramming and compiler infrastructure
- 6Familiarity with data modeling and intermediate representation for compiler passes
- 7Background in test‑driven development and adaptive unit testing
- 8Excellent attention to detail and commitment to high‑quality design
- 9Ability to work effectively in cross‑functional teams
- 10Knowledge of RISC‑V architecture and its extensions
- 11Exposure to verification principles testbenches UVM and coverage analysis
- 12Experience with version control systems such as Git GitHub and issue tracking tools like Jira Confluence
Salary Insight
$159 - $194k per year
Location
Required Skills
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