Principal Interconnect Design Engineer SiFive
Overview
Lead hardware engineer at SiFive to design industry-leading CPU and interconnect IP driving RISC-V adoption. Build highly-configurable hardware generators using Chisel Scala to create scalable processors and TileLink interconnects. Accelerate time-to-market while maintaining exceptional performance and quality.
What You'll Do11
- 1Architect and implement enhanced TileLink interconnect cache controllers and protocol bridges as RTL generators in Chisel
- 2Design self-configuring infrastructure components that optimally connect diverse subsystems
- 3Enhance designs for superior multi-core coherence and performance
- 4Integrate new content into Chisel/FIRRTL framework for automated documentation generation and testing
- 5Perform sandbox verification and collaborate with verification team on test plan execution
- 6Share knowledge through comprehensive documentation and collaborative design practices
- 7Develop scalable hardware abstractions using templated metaprogramming and functional programming techniques
- 8Create and maintain high-quality RTL code in Verilog SystemVerilog or VHDL
- 9Contribute to compiler infrastructure for domain-specific language development
- 10Implement adaptive unit tests and participate in cross-functional teamwork
- 11Maintain attention to detail while working toward impactful hardware solutions
Requirements10
- 15+ years building ETL pipelines with Spark and Airflow
- 2Experience with NoC or other interconnect fabrics and industry bus protocols (AXI AHB APB CHI CXL UCIe)
- 3Strong software engineering background including OOP AOOP functional programming templated metaprogramming
- 4Proficiency with hardware design in Verilog SystemVerilog or VHDL
- 5Knowledge of compiler infrastructures for DSLs and intermediate representations
- 6BS/MS in EE CE CS or related field with strong academic foundation
- 7Familiarity with Git/Github Jira Confluence collaboration tools
- 8Experience with Scala/Chisel Bluespec or similar language/DSL for configurable hardware
- 9Understanding of RISC-V architecture and TileLink specifications
- 10Ability to work effectively in a fast-paced collaborative environment
Salary Insight
Salary not disclosed in listing
Location
Required Skills
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