Waymo
WaymoVerified Source

SoC Architect Waymo

251K–310K
Partially · San Jose, California
Posted August 1, 2026
payroll

Overview

Waymo's Compute Team seeks a SoC Architect to define next‑generation autonomous vehicle SoCs. This hybrid role reports to an Engineering Director and leads microarchitecture specification, hardware‑software integration, and performance optimization. The ideal candidate owns major design blocks and drives delivery from concept to production.

What You'll Do7

  • 1Define architecture and microarchitecture for Waymo's next‑generation autonomous vehicle SoCs translating system‑level requirements into detailed hardware specs and RTL implementation
  • 2Lead microarchitecture and implementation of IPs and subsystems including high‑performance cache hierarchies Network‑on‑Chip interconnects and custom accelerators
  • 3Collaborate with Architects Firmware and Software teams to drive feature closure and develop microarchitecture specifications
  • 4Perform power area and performance exploration and optimization of digital designs
  • 5Mentor engineers and guide vendor relationships using innovative ideas to solve design challenges evaluate and select third‑party IP and ensure timely tapeout
  • 6Own major design blocks or subsystems with proven technical leadership from concept to production
  • 7Drive cross‑functional initiatives to integrate hardware firmware and software for maximum performance

Requirements6

  • 1MS degree in Computer Engineering Electrical Engineering or related field or equivalent practical experience
  • 210+ years industry experience in ASIC SoC digital design microarchitecture and integration including ownership of major design blocks or subsystems
  • 3Proven track record of technical leadership driving design and execution from concept to production and hands‑on experience with successful ASIC tapeouts
  • 4Deep expertise in SystemVerilog for RTL design microarchitecture and integration strong understanding of computer architecture memory systems cache coherence and high‑speed on‑chip interconnects
  • 5Fluency in Python C++ for architectural modeling design automation and debugging strong debug and problem‑solving skills with ability to root‑cause complex issues across hardware and software boundaries
  • 6PhD degree preferred knowledge of hardware/software co‑design arithmetic units processor design accelerators bus architectures fabrics NoC memory hierarchies high performance low power design techniques AI tools experience with Chisel Scala or other hardware DSLs

Salary Insight

$251 - $310k per year

Location

Typepartially
LocationSan Jose, California

Required Skills

SystemVerilogPythonC++RTL designMicroarchitectureNoCHardware/software co-designChisel
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