Senior Lead Memory Circuit Design Engineer, Mixed-Signal & NVM
Overview
Own a production-grade memory subsystem within an advanced mixed-signal SoC at scale. Drive architecture to tapeout across memory arrays, read/write circuitry, sensing, reference generation, and datapath integration. Collaborate with Analog, Digital/RTL, Verification, and Layout teams while mentoring junior engineers to hit milestones through multiple tapeouts. This role is distinguished by end-to-end ownership of memory subsystems and cross-functional leadership in a high-performance AI edge/data-center context.
What You'll Do10
- 1Own full memory subsystem delivery from specification architecture circuit design verification and signoff to tapeout
- 2Define and refine memory block requirements aligned to full-chip specifications for performance power robustness and testability
- 3Circuit verification planning SPICE testbenches PVT/temperature sweeps Monte Carlo mismatch reliability checks
- 4Review Chip level STA timing violations related to the memory and implement margin measures
- 5Waveform review and documentation of summary findings
- 6Partner with Layout on floorplan constraints parasitic-aware design EM/IR density/fill antenna and signoff closure
- 7Coordinate cross-functional reviews manage risks and mentor junior engineers to achieve milestones
- 8Collaborate across analog digital/RTL verification and layout to ensure schedule-driven milestones
- 9Ensure robust post-silicon characterization and debug readiness
- 10Mentor engineers and maintain quality and schedule through multiple tapeouts
Requirements10
- 1BSEE/MSEE/PhD in Electrical Engineering or related field
- 215+ years of memory circuit design experience including SRAM and non-volatile memory technologies
- 3Proven record of multiple successful tapeouts with block or subsystem ownership
- 4Deep expertise in mixed-signal design fundamentals and memory read/write design tradeoffs
- 5Strong experience with sense amplifier design reference generation and variation-aware margin analysis
- 6Experience with address decoders timing control sequencing and datapath integration
- 7Hands-on proficiency with Cadence and Synopsys design flows and SPICE-class simulation tools PrimeSim HSPICE Spectre
- 8Ability to lead cross-functional execution and mentor engineers while maintaining quality and schedule
- 9Experience with advanced non-volatile and resistive memory architectures including crosspoint-style arrays
- 10Prior work on MRAM and/or RRAM designs silicon characterization and post-silicon debug
Salary Insight
$150 - $200k per year
Location
Required Skills
Similar open positions
Explore active roles that match your skills and interests.
100 Intel Corporation
VerifiedAdvanced Memory Circuit Design Engineer at Intel
Lead memory technology innovation driving high-performance embedded memory solutions. Own memory pathfinding and PPA optimization to accelerate product market entry. Shape next generation memory architectures using advanced CMOS processes. Collaborate with cross-functional experts to deliver industry-leading memory collaterals.
1000 Micron Technology, Inc.
VerifiedHBM Memory Design Architect, PhD
You will own the design and analysis of digital and analog circuits for HBM memory products, simulating and optimizing DRAM circuits at block and full-chip level. You will join a highly innovative team using state-of-the-art memory technologies to develop the most advanced HBM products in the industry. Your work will directly influence future memory architectures, with a focus on AI-driven design research. This role offers the chance to conduct pathfinding for next-generation HBM solutions and contribute to groundbreaking innovations at Micron.
Senior CMOS Test and Validation Lead - Analog Mixed-Signal Raxium
Senior CMOS Test and Validation Lead drives bring-up characterization and HVM release for next-gen Analog Mixed-Signal ASICs. This role bridges design DFT and product engineering to ensure zero-defect quality and optimized cost-of-test. The candidate leads a team through complex yield and performance bottlenecks while partnering with IC design and DFT teams.
Sandisk
VerifiedTechnical Program Manager - Semiconductor & Memory Test Solutions
Lead end-to-end program management for semiconductor and memory test solutions across product lifecycle. Drive cross-functional programs from concept through production deployment. Manage integrated program plans schedules resources budgets and risks. Provide executive-level status reports and coordinate with ASIC SoC IP memory design and product teams. Differentiate by shaping test solutions that enable global supply chain access to Flash memory.
Efficient Computer
VerifiedLead Physical Design Engineer SOC Top Lead
Efficient develops energy efficient general purpose computer processor. Lead engineer drives SOC top for next generation SoCs. Own full chip from block integration to tapeout ready GDS. Influence product evolution from development to market release. Shape future of computing at the edge.
Everforth, Cybercoders
VerifiedSenior Electrical Engineer, Mixed-Signal PCB & FPGA Design
Lead design and development of high-reliability mixed-signal electronic systems from concept to production, focusing on high-density PCB design, FPGA integration, and embedded software. Drive architectural decisions, collaborate with cross-functional teams, and mentor junior engineers. Ensure compliance with ISO 13485 and IEC 60601 standards. This role offers ownership of complex hardware, direct impact on product launch, and opportunities to shape engineering practices.