DFT Engineer, SoC/ASIC ATPG & MBIST
Overview
As a DFT Engineer, you will own scan insertion, ATPG pattern generation, and MBIST validation for complex SoC and ASIC designs. You will collaborate with RTL and physical design teams to ensure high test coverage and silicon bring-up success. This role focuses on solving intricate DFT challenges at scale, directly impacting product quality. You will drive test strategy from block level to full-chip integration, using hands-on expertise in Design for Test methodologies.
What You'll Do7
- 1Integrate scan chains and implement DFT logic in SoC and ASIC designs, ensuring controllability and observability.
- 2Generate ATPG patterns for stuck-at and transition faults, analyzing coverage and resolving test failures.
- 3Debug ATPG mismatches using EDA tools and waveform analysis, driving fixes in RTL or test logic.
- 4Architect and validate MBIST controllers for embedded memories, including repair and diagnostics.
- 5Develop and execute IO test strategies for interface protocols, covering pin-level validation and AC/DC characteristics.
- 6Collaborate with physical design to close timing and area constraints for DFT insertions.
- 7Support silicon bring-up, performing pattern validation and correlating tester results with simulation.
Requirements8
- 15+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs.
- 2Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing.
- 3Proven expertise in ATPG pattern generation, analysis, and debug.
- 4Experience with MBIST, including memory test architectures and diagnostics.
- 5Knowledge of IO Test methodologies for interface and pin level validation.
- 6Hands-on experience with EDA tools such as Tessent, Modus, or DFTMAX.
- 7Proficiency in scripting with Tcl, Python, or Perl for automation and flow optimization.
- 8Solid understanding of Verilog/VHDL and digital design concepts.
Salary Insight
$70k per year
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