Senior HBM ESD Latch-Up Architect 50-60 chars
Overview
Lead definition and implementation of ESD and latch-up protection strategies for next generation HBM products across advanced nodes and 3D integration. Own product reliability from architecture through silicon validation. Shape technical direction while solving system-level ESD challenges. Support AI-enabled solutions that improve efficiency and decision-making. This role defines end-to-end protection across base die DRAM stacks and interconnects. Develop standards drive correlation between design assumptions and field reliability. Partner with foundry and packaging teams on ESD challenges.
What You'll Do5
- 1Define end-to-end ESD and latch-up architecture across base die DRAM stacks and interconnects
- 2Develop protection strategies for high-speed I/O TSV interfaces and advanced packaging
- 3Establish ESD/LUP standards rule decks and signoff criteria
- 4Drive correlation between design assumptions silicon validation and field reliability
- 5Partner with foundry and packaging teams on system-level ESD challenges
Requirements7
- 1MS or PhD in Electrical Engineering or related field or equivalent practical experience 10+ years in ESD and latch-up design and reliability
- 2Expertise in advanced CMOS technologies such as FinFET or GAA
- 3Experience with 3D IC TSV or die-to-die interfaces
- 4Background in ESD device or circuit design
- 5Experience developing PDK collateral or ESD rule decks
- 6Proven track record debugging silicon failures related to ESD or latch-up
- 7Demonstrated technical leadership across cross-functional teams
Salary Insight
$177 - $334k per year
Location
Required Skills
Similar open positions
Explore active roles that match your skills and interests.
Everforth, Cybercoders
VerifiedSenior Electrical Engineer, Mixed-Signal PCB & FPGA Design
Lead design and development of high-reliability mixed-signal electronic systems from concept to production, focusing on high-density PCB design, FPGA integration, and embedded software. Drive architectural decisions, collaborate with cross-functional teams, and mentor junior engineers. Ensure compliance with ISO 13485 and IEC 60601 standards. This role offers ownership of complex hardware, direct impact on product launch, and opportunities to shape engineering practices.
Monolithic Power Systems Inc.
VerifiedDesign Engineer, Analog & Mixed-Signal IC Design
You will design analog and mixed-signal ICs for power management products using sub-micron BiCMOS/DMOS technologies. You will own circuit synthesis from transistor to system level, simulation, and layout supervision. You will collaborate with senior designers, ATE, and applications engineers to bring products from concept to qualification. This role focuses on switching regulators, hot-swap eFuse, half-bridge drivers, and power management ICs for networking, server, and telecom markets.
1000 Micron Technology, Inc.
VerifiedHBM Memory Design Architect, PhD
You will own the design and analysis of digital and analog circuits for HBM memory products, simulating and optimizing DRAM circuits at block and full-chip level. You will join a highly innovative team using state-of-the-art memory technologies to develop the most advanced HBM products in the industry. Your work will directly influence future memory architectures, with a focus on AI-driven design research. This role offers the chance to conduct pathfinding for next-generation HBM solutions and contribute to groundbreaking innovations at Micron.
1000 Micron Technology, Inc.
VerifiedHBM SoC RTL Design Engineer at Micron Technology
Lead the design and implementation of RTL for SoC-level blocks within HBM logic dies. Integrate internal and third-party IP while collaborating with cross-functional teams to deliver high-performance SoC solutions. Drive AI tool adoption and contribute to design documentation and validation processes. Seeking a candidate with strong SystemVerilog expertise and hands-on experience in SoC integration methodologies.
1000 Micron Technology, Inc.
VerifiedSoC Physical Design Engineer
Senior Member of Technical Staff leads physical design of SoC logic/base die from netlist to GDSII within Heterogeneous Integration Group. Owns implementation across multiple product generations and drives performance power area targets.
Efficient Computer
VerifiedLead Physical Design Engineer SOC Top Lead
Efficient develops energy efficient general purpose computer processor. Lead engineer drives SOC top for next generation SoCs. Own full chip from block integration to tapeout ready GDS. Influence product evolution from development to market release. Shape future of computing at the edge.