Senior Analog Engineering Manager at Renesas Electronics
Overview
Lead development of DDR5 and next-generation DDR6 PHY solutions for advanced SoCs. Manage end-to-end delivery of high-performance low-power DDR PHYs from architecture to silicon bring-up while shaping DDR6 signaling roadmap. Drive technical excellence and cross-functional collaboration.
What You'll Do11
- 1Own and guide architecture design implementation of DDR5 PHYs and contribute to DDR6-ready systems
- 2Provide technical oversight for analog and mixed-signal blocks including high-speed datapaths equalization termination and training circuits
- 3Lead post-silicon bring-up characterization debug and yield improvement initiatives
- 4Partner with Digital PHY controller teams package PCB SI/PI validation and product program management
- 5Interface with foundries IP vendors and standards bodies to ensure delivery and future readiness
- 6Establish robust design methodologies improve simulation accuracy and silicon debug efficiency
- 7Drive long-term DDR5 sustainment and DDR6 technology roadmap planning
- 8Mentor and build analog mixed-signal engineering teams
- 9Set technical direction performance expectations and development plans for senior engineers
- 10Balance schedule quality and risk across DDR5/DDR6 PHY execution
- 11Anticipate and address challenges related to data-rate scaling power efficiency and advanced processes
Requirements10
- 1Bachelor’s or Master’s degree in Electrical Engineering PhD preferred
- 212+ years analog/mixed-signal IC design experience focusing on high-speed memory interfaces
- 35+ years people-management and technical leadership experience
- 4Proven delivery of DDR5 PHYs or late-stage DDR4 to DDR5 transitions
- 5Strong expertise in high-speed IO design signal integrity PLL/DLL low-jitter clocking mixed-signal verification and advanced CMOS process considerations
- 6Direct involvement in DDR6 architectural studies or early-stage development
- 7Experience at advanced nodes 7nm 5nm and below
- 8Background in multi-generation memory PHYs or scalable PHY platforms
- 9Ability to lead teams delivering multiple concurrent tape-outs
- 10Excellent written and verbal communication skills across technical and executive audiences
Salary Insight
Salary not disclosed in listing
Location
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