Renesas ElectronicsVerified Source

Principal Digital Verification Engineer - DDR5 UVM | Renesas

Onsite · Austin, Texas
Posted August 7, 2026
payroll

Overview

You will own verification of DDR5 and DDR6 memory data buffer chips for AI datacenters. Your work drives bandwidth and power efficiency at massive scale. You lead UVM-based verification environments, mentor a team, and collaborate with design on testability. This role shapes next-gen memory interface products at Renesas in Austin, with direct impact on high-performance computing.

What You'll Do8

  • 1Build system-level and block-level verification environments for DDR5 data buffers using UVM methodology.
  • 2Drive the verification effort from test plan to coverage closure, defining strategy and executing tests.
  • 3Develop reusable, state-of-the-art testbench structures and optimize for performance and ease of use.
  • 4Own verification environments for assigned blocks, acting as the expert user for designated tools.
  • 5Mentor a team of verification engineers, providing technical guidance on UVM and verification best practices.
  • 6Collaborate with the design team to ensure testability and requirement alignment early in the design cycle.
  • 7Monitor coverage metrics and drive improvements to achieve functional and performance targets.
  • 8Report verification status and risks to management, ensuring transparent progress tracking.

Requirements8

  • 18+ years of experience with a Master's in Electrical Engineering, Computer Engineering, or equivalent.
  • 210+ years of experience with a Bachelor's in Electrical Engineering, Computer Engineering, or equivalent.
  • 35+ years hands-on verification of digital designs using UVM and SystemVerilog.
  • 4Experience verifying memory interface protocols like DDR5, DDR4, or LPDDR.
  • 5Proven track record of leading verification projects from planning to tape-out.
  • 6Strong debugging skills with simulation tools such as VCS, Questa, or Xcelium.
  • 7Experience with coverage-driven verification and functional coverage models.
  • 8Ability to mentor and technically lead a team of verification engineers.

Salary Insight

Salary not disclosed in listing

Location

Typeonsite
LocationAustin, Texas

Required Skills

UVM methodologyVerification planningTestbench developmentCoverage analysisDDR5DDR6Memory interface verificationFeature extraction
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