Staff Engineer Design Verification Engineering
Overview
Lead verification environments for ASIC SOC designs. Own creation of UVM-based verification ecosystems. Drive functional coverage analysis and metric tracking. Integrate third party and custom IPs within subsystem-level UVM frameworks. Collaborate across teams to ensure coverage closure and support post-silicon verification activities.
What You'll Do8
- 1Develop and execute UVM-based verification environments for block-level and full-chip ASIC SOC designs
- 2Create and implement verification plans including constrained-random and directed test cases
- 3Write and analyze functional coverage assertions and metrics to ensure thorough verification
- 4Integrate and verify third-party and custom IPs/VIPs within subsystem-level UVM environments
- 5Collaborate with design and cross-functional teams to review test plans resolve issues and ensure coverage closure
- 6Support post-silicon verification activities working with evaluation and applications engineering teams
- 7Automate simulation data analysis and model validation using scripting languages and design automation tools
- 8Partial telecommute benefit (2 days/week work from home)
Requirements6
- 1Master’s degree in Computer Science Computer Engineering Electrical Engineering or related field or equivalent foreign education
- 2Four years of experience as a Design Verification Engineer or related occupation performing IC design or validation
- 3Demonstrated expertise using metric-driven verification throughout the full lifecycle of design verification
- 4Expertise translating Design Verification requirements into robust DV environments and architecting coverage analysis
- 5Proficiency using UVM agents and integrating third-party or custom Verification IPs for stimulus sequences and functional checkers
- 6Experience debugging simulations and analyzing waveforms
Salary Insight
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