Design Engineer Sunnyvale CA | Verification & Design Team
Overview
Join our team as a Design Engineer Sunnyvale CA to develop and execute verification plans for RTL blocks/IPs. You will build and maintain SystemVerilog/UVM testbenches while driving functional coverage and assertion closure. This role offers a chance to work on cutting‑edge silicon verification projects and collaborate with innovative professionals.
What You'll Do6
- 1Develop and execute verification plans for RTL blocks/IPs across subsystems
- 2Build and maintain SystemVerilog/UVM testbenches and write directed and constrained‑random tests
- 3Drive functional coverage and SVA closure and run regression triage
- 4Perform power/performance measurements using PPA RTL and PtPx tools
- 5Create dashboards for tracking power/performance metrics and publish findings
- 6Debug RTL failures and provide actionable feedback to design and power‑modeling teams
Requirements5
- 1Proven SystemVerilog and UVM verification experience including testbench architecture sequences drivers monitors
- 2Strong functional coverage and constraint randomization and SVA skills
- 3Experience debugging RTL with VCS Xcelium Questa and waveform tools Verdi
- 4Working knowledge of RTL design principles and digital design fundamentals
- 5Proficiency in Python or Perl scripting for automation tasks
Salary Insight
$67k per year
Location
Required Skills
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