STA Engineer, Timing Closure & Signoff
Overview
Own timing constraints and drive block- and full-chip timing closure across all modes and corners for advanced-node SoC designs. You will collaborate with physical design, synthesis, and DFT teams to deliver silicon-ready signoff. This role offers direct impact on high-performance, low-power chips for a leading manufacturer. Your work ensures first-pass silicon success.
What You'll Do6
- 1Build and validate timing constraints for blocks and full chip using Synopsys PrimeTime.
- 2Drive closure across all modes and corners, fixing setup and hold violations.
- 3Collaborate with physical design and synthesis teams to resolve timing issues.
- 4Debug and fix constraint problems, including clock definitions and exceptions.
- 5Run and analyze timing reports, identifying critical paths and proposing fixes.
- 6Support DFT teams with scan mode timing and test coverage analysis.
Requirements6
- 15+ years in static timing analysis and timing signoff.
- 2Hands-on with Synopsys PrimeTime and Tempus.
- 3Experience with advanced nodes (7nm and below).
- 4Strong knowledge of timing closure techniques and constraints.
- 5Proficiency in TCL and Perl for scripting and automation.
- 6Bachelor's or Master's in Electrical Engineering or related field.
Salary Insight
$90 - $102k per year
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