SoC Physical Design Engineer PnR Apple Austin Texas
Overview
Lead the physical implementation of design partitions from netlist to tapeout for a complex SOC using innovative process technology. Drive best in class designs by collaborating with architecture CAD timing and logic design teams. Impact delivery at scale while contributing to Apple's mission of leaving the world better.
What You'll Do6
- 1Collaborate with logic design team to understand partition architecture and drive physical aspects early in the design cycle
- 2Complete netlist to GDS2 implementation for partitions meeting schedule and design goals
- 3Perform timing physical and electrical verification and drive signoff closure for partitions
- 4Resolve and improve design flow issues related to physical design identifying potential solutions and executing them
- 5Work with cross functional teams across various fields to achieve project objectives
- 6Drive optimization of physical design processes and methodologies
Requirements5
- 1Minimum BS Degree with 0+ years experience
- 2Basic understanding of logic gates
- 3Previous internship/co-op project work or relevant coursework in computer architecture VLSI design logic design or circuit design
- 4Strong teamwork skills with ability to collaborate across multiple functional areas
- 5Experience with Verilog VHDL Python Perl TCL or SPICE
Salary Insight
Salary not disclosed in listing
Location
Required Skills
Similar open positions
Explore active roles that match your skills and interests.
1000 Micron Technology, Inc.
VerifiedSoC Physical Design Engineer
Senior Member of Technical Staff leads physical design of SoC logic/base die from netlist to GDSII within Heterogeneous Integration Group. Owns implementation across multiple product generations and drives performance power area targets.
Apple
VerifiedASIC Design and Integration Engineer - Silicon Security
Apple Silicon Security team seeks a driven ASIC Design Engineer to build secure subsystems protecting the entire Apple SoC. Responsible for designing hardware defenses against side channel attacks and ensuring integrity of sensitive customer data across product lines. Role involves architecting micro-architecture RTL design and integration of secure subsystems while collaborating with Platform Architecture and Design Verification teams.
Efficient Computer
VerifiedLead Physical Design Engineer SOC Top Lead
Efficient develops energy efficient general purpose computer processor. Lead engineer drives SOC top for next generation SoCs. Own full chip from block integration to tapeout ready GDS. Influence product evolution from development to market release. Shape future of computing at the edge.
Saksoft
VerifiedAnalog Layout Engineer, High-Speed IC Design
Own analog layout design for high-speed ICs at Apple-scale complexity. Work with a cross-functional team of silicon engineers in Cupertino. Drive layout from schematic to tapeout, owning critical blocks. 6+ years of analog layout experience required. Cadence Virtuoso and Calibre verification are core to this role.
CPU Physical Design Engineer - Google Silicon
Own block-level physical design for Google's custom silicon, from synthesis through signoff, targeting high-performance, low-power CPUs at 5nm and below. Collaborate with RTL, Architecture, and DFT teams to align constraints and resolve timing, congestion, and power issues. Drive design convergence with industry-standard tools like Synopsys and Cadence. This role requires deep expertise in Place & Route and STA to deliver silicon that powers Google's direct-to-consumer products.
191 Altera Corporation
VerifiedPhysical Design Engineer at Altera Corporation
We seek a Physical Design Engineer to lead chip and block-level design for custom IP and SoC projects. This role drives end-to-end physical implementation from RTL to GDSII while ensuring timing closure power optimization and signoff. You will collaborate with cross-functional teams to deliver high-quality silicon for cutting-edge FPGA technologies.