Physical Design Engineer, ASIC/SoC Synthesis & Floorplanning (Contract)
Overview
Own the physical design flow for high-performance ASIC and SoC projects targeting advanced process technologies. Lead synthesis, floorplanning, placement, routing, and timing optimization to meet performance and area goals at scale. Collaborate with RTL, design verification, and backend teams to deliver silicon closing timing and power targets on a contract basis.
What You'll Do5
- 1Build RTL synthesis and physical implementation flows for complex ASIC and SoC designs
- 2Design floorplans and placement strategies to optimize timing and power in advanced nodes
- 3Ship timing-closed, area-efficient layouts through iterative optimization and verification
- 4Drive performance tuning and optimization across RTL, synthesis, and back-end stages
- 5Collaborate with cross-functional teams to ensure silicon quality and schedule adherence
Requirements5
- 15+ years building IC physical design flows for ASIC/SoC projects
- 2Experience with RTL synthesis, floorplanning, placement, routing, and timing optimization
- 3Knowledge of timing closure, power analysis, and sign-off processes in backend flows
- 4Strong collaboration skills with RTL, DRC, LVS, and EDA toolchains
- 5Contract role based in San Jose, CA with onsite requirements
Salary Insight
$75 - $85k per year
Location
Required Skills
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